Topic 2e, Reading 3: The Cycle in Action

From Abstract to Concrete

Reading 2 gave you the vocabulary and the big picture: the CPU fetches an instruction from RAM, decodes it, executes it, and repeats. That loop is real — but it can feel abstract until you actually watch it happen.

In this reading, we will trace the FDE cycle through a short, complete program. The program has one job: compute the average of two quiz scores and store the result. Nothing fancy — but it will require the CPU to load values, add them, divide, and store the answer. By the end, you will have followed every instruction from RAM through the CPU and back.

Setting the Stage

Before we trace a single instruction, we need to know what is in memory when the program starts. Our program uses a simplified machine language — small enough to be readable, realistic enough to show you what real CPUs do.

The CPU has four general-purpose registers, which we will call R1, R2, R3, and R4. Think of them as four sticky notes sitting right next to the CPU — small, fast, and temporary. Values have to be copied into a register before the CPU can work with them.

RAM is organized into numbered addresses. Each address holds one value. At the start of our program, RAM looks like this:

RAM Address	Contents	What It Is
`A0`	`LOAD R1, B0`	Instruction 1 (the program starts here)
`A1`	`LOAD R2, B1`	Instruction 2
`A2`	`ADD R3, R1, R2`	Instruction 3
`A3`	`DIV R4, R3, 2`	Instruction 4
`A4`	`STORE R4, B2`	Instruction 5
`B0`	`84`	Quiz Score 1 (data)
`B1`	`92`	Quiz Score 2 (data)
`B2`	`???`	Result slot (empty at the start)

The program counter (PC) starts pointing at address A0 — the first instruction. All four registers (R1-R4) are empty. The cycle is ready to begin.

Note on addresses: The labels like A0 and B0 are just convenient, human-readable shorthand for RAM addresses. In a real machine these would be numeric addresses like 10100000 and 10110000. The names here simply keep instructions and data visually separate.

Instruction 1 — Load the First Score

The PC points to A0. Here is what the CPU does through all three stages of the FDE cycle for this instruction.

Stage	What Happens	Data Movement
Fetch	The CPU reads address `A0` from RAM and copies the instruction `LOAD R1, B0` into the Instruction Register. The PC advances to `A1`.	RAM[A0] → IR
Decode	The Control Unit reads the IR and determines: this is a LOAD instruction. Copy the value at RAM address `B0` into register R1.	(no data moves yet)
Execute	The value at RAM address `B0` — which is `84` — is copied into register R1.	RAM[B0] → R1

State after Instruction 1: R1 = 84. Everything else is unchanged. The PC is now pointing at A1.

Instruction 2 — Load the Second Score

The PC now points to A1. The cycle repeats.

Stage	What Happens	Data Movement
Fetch	The CPU reads address `A1` from RAM and copies `LOAD R2, B1` into the IR. The PC advances to `A2`.	RAM[A1] → IR
Decode	The Control Unit reads the IR: another LOAD. Copy the value at `B1` into register R2.	(no data moves yet)
Execute	The value at RAM address `B1` — which is `92` — is copied into register R2.	RAM[B1] → R2

State after Instruction 2: R1 = 84, R2 = 92. The PC is now pointing at A2.

Instruction 3 — Add the Two Scores

Both scores are now in registers. The CPU can finally do some arithmetic. This is the first instruction that involves the ALU.

Stage	What Happens	Data Movement
Fetch	The CPU reads address `A2` from RAM and copies `ADD R3, R1, R2` into the IR. The PC advances to `A3`.	RAM[A2] → IR
Decode	The Control Unit reads the IR: an ADD. Send the values in R1 and R2 to the ALU, and put the result in R3.	(no data moves yet)
Execute	The values in R1 (84) and R2 (92) are sent to the ALU. The ALU adds them: 84 + 92 = 176. The result is placed into R3.	R1, R2 → ALU → R3

State after Instruction 3: R1 = 84, R2 = 92, R3 = 176. The PC is now pointing at A3.

Instruction 4 — Divide by 2

We have the sum. Now the ALU divides it by 2 to produce the average.

Stage	What Happens	Data Movement
Fetch	The CPU reads address `A3` from RAM and copies `DIV R4, R3, 2` into the IR. The PC advances to `A4`.	RAM[A3] → IR
Decode	The Control Unit reads the IR: a DIV. Divide the value in R3 by the constant 2, and put the result in R4.	(no data moves yet)
Execute	The value in R3 (176) is sent to the ALU along with the constant 2. The ALU divides: 176 ÷ 2 = 88. The result is placed into R4.	R3 → ALU → R4

State after Instruction 4: R1 = 84, R2 = 92, R3 = 176, R4 = 88. The PC is now pointing at A4.

Instruction 5 — Store the Result

The average is sitting in R4, but registers are temporary. If the power flickered or another program needed R4, the value would be gone. The final instruction writes the result back to RAM, where it will persist.

Stage	What Happens	Data Movement
Fetch	The CPU reads address `A4` from RAM and copies `STORE R4, B2` into the IR. The PC advances to `A5`.	RAM[A4] → IR
Decode	The Control Unit reads the IR: a STORE. Copy the value in R4 into RAM address `B2`.	(no data moves yet)
Execute	The value in R4 (88) is written to RAM address `B2`. The result slot now holds the computed average.	R4 → RAM[B2]

State after Instruction 5: RAM address B2 now holds 88. The program is complete.

The Full Picture

Here is what the program accomplished, from start to finish. Five instructions, five trips through the FDE cycle, one computed average.

Instruction	Operation	Net Effect
`LOAD R1, B0`	Load	R1 ← 84
`LOAD R2, B1`	Load	R2 ← 92
`ADD R3, R1, R2`	Add	R3 ← 176
`DIV R4, R3, 2`	Divide	R4 ← 88
`STORE R4, B2`	Store	RAM[B2] ← 88

Notice the overall shape: the program begins by moving data into the CPU (two LOADs), does its arithmetic in the middle (ADD, then DIV), and ends by moving the result back out to RAM (STORE). That in-compute-out pattern is the skeleton of nearly every computation a CPU performs.

Now You Try

A different program starts with the following RAM contents. The program counter begins at address A0 and all registers are empty.

RAM Address	Contents
`A0`	`LOAD R1, B0`
`A1`	`LOAD R2, B1`
`A2`	`ADD R3, R1, R2`
`A3`	`STORE R3, B2`
`B0`	`30`
`B1`	`15`
`B2`	`???`

Trace the FDE cycle for each of the four instructions. For each one, identify what happens at the Fetch, Decode, and Execute stages, and what data movement occurs. What value ends up at RAM address B2 when the program finishes?

Show Answer

Instruction 1 — LOAD R1, B0
Fetch: RAM[A0] → IR. PC advances to A1.
Decode: CU identifies a LOAD; copy RAM[B0] into R1.
Execute: RAM[B0] → R1. R1 = 30.

Instruction 2 — LOAD R2, B1
Fetch: RAM[A1] → IR. PC advances to A2.
Decode: CU identifies a LOAD; copy RAM[B1] into R2.
Execute: RAM[B1] → R2. R2 = 15.

Instruction 3 — ADD R3, R1, R2
Fetch: RAM[A2] → IR. PC advances to A3.
Decode: CU identifies an ADD; send R1 and R2 to the ALU, result into R3.
Execute: R1 + R2 = 30 + 15 = 45. R3 = 45.

Instruction 4 — STORE R3, B2
Fetch: RAM[A3] → IR. PC advances to A4.
Decode: CU identifies a STORE; copy R3 into RAM[B2].
Execute: R3 → RAM[B2]. RAM[B2] = 45.

Final answer: RAM address B2 holds 45. This program loaded two values (30 and 15), added them, and stored the sum. ✓

What This Means for Your Classroom

You have just done something most people never do: you followed actual data through a CPU, one instruction at a time. The scale in real hardware is vastly larger — billions of instructions per second, billions of transistors — but the logic is the same loop you just traced five times.

For K-12 students, this kind of concrete tracing is often the moment hardware stops being magic and starts making sense. The abstraction of "the computer just does it" gives way to a clearer picture: instructions move, data moves, the CPU follows a disciplined sequence. That is a powerful shift, regardless of grade level.

As you prepare to discuss these ideas with students, consider: which part of this trace felt most surprising or clarifying to you? That reaction is often a good signal about where your students will need the most support.