Topic 2e – The Fetch-Decode-Execute Cycle

Fetch. Decode. Execute. Repeat. Three steps, billions of times a second, making everything work.

Learning Objectives

By the end of this topic, you should be able to:

Learning Activities

To help you meet the learning objectives, we have prepared a combination of readings, activities, and videos.

Course Readings

These reading were designed to introduce the course topics to an audience of educators. They should be considered "required" and read in order.

Supplemental Readings

Some participants find it helpful to read about a topic from a source written for a slightly more technical audience. These supplemental readings cover similar material as the course readings but may not fully align with the course learning objectives. Use them as an optional complement to your study, not a substitute for the course readings.

Lesson Videos

These videos support the readings above and may present the material with some deeper connections and worked examples.

Checking for Understanding, Questions

Review the Learning Objectives at the top of this page. You will be asked to demonstrate these skills on this week's competency demo. To check your understanding, try the following questions. Try each one on your own before looking at the answer key. It is completely fine if you need to revisit the readings as you work through these questions.

Storage and Setup

  1. In your own words, explain why a program must be loaded from secondary storage into RAM before the CPU can run it. What property of RAM makes this necessary, and what property of secondary storage makes it the right place to keep programs long-term?
  2. When you launch a program and then lose power before saving your work, why is your unsaved work gone but the original program file is not? Use what you know about RAM and secondary storage to explain.

CPU Components

  1. What does the Program Counter hold, and how does it change during the Fetch stage?
  2. What is the difference between the Instruction Register and a general-purpose register? What kind of information lives in each one?
  3. The Control Unit does not perform calculations. What does it do instead, and why is it essential to the cycle?

Tracing the Cycle

  1. A program begins with the following contents in RAM. The PC starts at address A0 and all registers are empty. Trace the FDE cycle for each instruction, and state the value that ends up at RAM address B2 when the program finishes.
    • A0: LOAD R1, B0
    • A1: LOAD R2, B1
    • A2: ADD R3, R1, R2
    • A3: STORE R3, B2
    • B0: 17
    • B1: 25
    • B2: ???

Checking for Understanding, Answers

You can begin by comparing your answers to the following answer key.

Show Answer Key

Storage and Setup

  1. RAM is directly addressable by the CPU — the CPU can fetch any byte from RAM in nanoseconds. Secondary storage (HDD or SSD) is far too slow for the CPU to read instruction by instruction during execution. RAM is also volatile (loses its contents when power is off), which is why it only holds the active program. Secondary storage is persistent (retains data without power), making it the right long-term home for programs and files.
  2. The program file lives on secondary storage and is not changed by running the program — it is just read into RAM. Your unsaved work existed only in RAM, which is volatile. When power is cut, RAM loses its contents immediately. The original program file on secondary storage is unaffected because nothing wrote changes back to it. This is why "save early, save often" exists as advice.

CPU Components

  1. The Program Counter holds the memory address of the next instruction to be fetched. During the Fetch stage, the CPU uses the address in the PC to retrieve that instruction from RAM, then increments the PC (adds 1, or the instruction size) so it points to the following instruction, ready for the next cycle.
  2. The Instruction Register (IR) holds the current instruction being executed — the raw binary instruction fetched from RAM. It is a temporary holding area for the instruction itself, not for data. A general-purpose register (R1, R2, R3, etc.) holds data values that the CPU is currently working with — numbers being added, addresses being computed, results being built. The IR holds "what to do"; general-purpose registers hold "what to do it with."
  3. The Control Unit reads the instruction in the IR, figures out what it means (decoding), and then coordinates all the activity needed to carry it out: telling the ALU what operation to perform, directing data movement between registers and RAM, updating the Program Counter, and managing timing. Without the Control Unit, the ALU would have no direction and data would have nowhere to go.

Tracing the Cycle

  1. Step-by-step trace:
    PCInstructionEffect
    A0LOAD R1, B0R1 ← 17 (value at B0)
    A1LOAD R2, B1R2 ← 25 (value at B1)
    A2ADD R3, R1, R2R3 ← 17 + 25 = 42
    A3STORE R3, B2B2 ← 42 (value in R3)
    The value at RAM address B2 when the program finishes is 42.

If you still have questions or concerns you can use the videos below to try and further your understanding.

Extend Your Learning

The following resources go a little deeper on topics we touched on but did not fully explore in the readings. These are entirely optional — none of this material appears on the Competency Demo — but each one is a natural "next question" from something covered this week.

  • Pipelining: doing multiple things at once
    Modern CPUs do not wait for one instruction to complete all three FDE stages before starting the next. Pipelining overlaps the stages of multiple instructions — while one instruction is being executed, the next is being decoded, and the one after is being fetched. This Computer Hope article explains pipelining clearly and introduces why it dramatically increases throughput.
    Pipelining — Computer Hope
  • Branch prediction and the Spectre/Meltdown vulnerabilities
    When the CPU encounters a conditional instruction, it may not know which path to take until after decoding. Modern CPUs guess and speculatively execute instructions before confirming the guess was correct. This optimization — branch prediction — turned out to create a serious security vulnerability. This accessible article from The Verge covers what Spectre and Meltdown are and why they arise directly from how modern CPUs are optimized.
    Spectre and Meltdown Explained — Medium
  • Machine language and assembly
    The LOAD, STORE, ADD, and other instructions in this topic are a simplified model of real machine language. Real CPUs have instruction sets with dozens or hundreds of operations, each encoded as a specific bit pattern. Assembly language gives each bit pattern a human-readable name. This introduction from Tutorials Point shows what real x86 assembly looks like and how it relates to the concepts traced this week.
    Assembly Language Introduction — Tutorials Point